1. Field of the Invention
The present invention relates to a process for fabricating thin film transistors, and more particularly to a process for fabricating thin film transistors (hereinafter called "TFT") at a low temperature, the TFTs being adapted for use in display devices and image sensors.
2. Description of the Prior Art
TFTs used for driving liquid crystal display devices and image sensors are fabricated in the same manner as the IC fabricating process. The ICs must be processed at about 1,000.degree. C. so as to effect crystallization, formation of insulating layers and activation of impurities, which requires that the substrate on which IDs are formed must be selected from materials which can withstand high temperatures. The commonest material is quartz. Such a requirement makes it difficult to use a large substrate on which ICs are formed. In order to solve the problems arising at high temperatures, amorphous or polycrystalline substance is used as a starting material which is crystallized by the solid phase growth or by laser annealing.
A TFT is a MOS type transistor. The performances of transistors depend upon the interface condition of the gate insulating layer and the semiconductor layer. When transistors are processed at low temperatures, the gate insulating layers are also processed at equally low temperatures.
Thin semiconductor layers are formed in a desired shape on a substrate, and subjected to surface treatment with the use of hydrofluoric acid, etc. Then, gate insulating layers are formed by sputtering or by a CVD method. These methods are not appropriate for reducing the interfacial level density for an unkown reason. The reason has been investigated. The investigation teaches that thin semiconductor layers should be followed by the formation of gate insulating layers without pause before the thin semiconductor layers are exposed to atmosphere.
In order to improve the performance of TFTs formed at low temperatures, it is necessary to reduce the interfacial level density between the semiconductor and gate insulating layers. In order to achieve this, the formation of thin semiconductor layers must be followed by the overlaying of gate insulating layers. To make the overlying layers as a TFT, the layer to be overlaid is formed in a desired island-shaped pattern in which the sides of the semiconductor layer are exposed outside. If the gate electrode is formed under this condition, the exposed sides of the semiconductor layer and the gate electrode are likely to come into contact with each other, thereby increasing the current leak. In order to prevent this current leak, it is required to cover the exposed sides of the semiconductor layer with an insulating layer 8 as shown in FIG. 9, prior to the formation of the gate electrode. In FIG. 9, an insulating substrate 1 on which a semiconductor layer 2, a gate insulating layer 3, and a gate electrode 4 overlap one above another. If the insulating layer 8 is made of SiO.sub.2, which is a material in common use for making gate insulating layers, the SiO.sub.2 of the gate insulating layer 3 is simultaneously etched. This simultaneous etching leaves the insulating layer 8 from shaping, and even if SiO.sub.2 and SiO.sub.2 have a large etching selective ratio, the simultaneous fabrication by etching is difficult. A PSG is known in the art which is fabricated by doping the SiO.sub.2 of an insulating layer with phosphorus. The larger the amount of the added phosphorus is, the larger the selective ratio becomes, but the phosphorus diffuses from the sides of the semiconductor layer 2, thereby changing the characteristics of the thin film transistor (TFT).